EDN

DDR-differential-clock source on SOC drives two DDR-memory chips

Many system engineers assume that a differential-clock source should drive just one chip. If a system design requires driving two DDR-memory chips, however, the design would inevitably need a ...
Electronic Design

DDR3 and DDR2 Memory IP Bolsters SoC Designs

A full range of DesignWare DDR intellectual property (IP) is available for systems-on-a-chip (SoCs) that require an interface to high-performance DDR3, DDR2, and DDR memory subsystems. The DesignWare ...
Design-Reuse

Toshiba Delivers DFI-Compatible DDR PHY to Speed Custom SoC Memory System Designs

New PHY Interoperates with Denali DDR Controller for Reduced Development Costs and Accelerated Time-to-Market PALO ALTO, Calif. -- Nov. 13, 2007 -- Denali Software, Inc., today announced the ...
Design-Reuse

Synopsys Launches Full Range of Silicon-Proven DDR3 and DDR2 IP Solutions for SoC Designs

High-Performance DesignWare IP Supports Speeds Up to 1600 Mbps MOUNTAIN VIEW, Calif. -- Aug. 13, 2008-- Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and ...
Business Wire

Silicon Valley Startup Granted US Patent on Critical DDR2/DDR3 Timing Innovation for Chip Designs

SANTA CLARA, Calif.--(BUSINESS WIRE)--Uniquify, a Silicon Valley semiconductor IP start-up (http://www.uniquify.com), today announced that it has been granted a ...
Electronic Design

Leverage High-Frequency Source-Synchronous Memory in SoC Design

Download this article in PDF format. Today’s embedded systems require high external memory bandwidth to achieve fast boot time and application loading time with minimal cost. Historically, ...
Embedded

Using multi-bit flip-flop custom cells to achieve better SoC design efficiency

System-on-chip (SoC) designs are becoming more and more complex, by whatever means you measure it: power domains, gate count, packing densities, heat dissipation capacities, etc. At such high packing ...
Semiconductor Engineering

How To Safeguard Memory Interfaces By Design

In 2017, the credit bureau Equifax announced that hackers had breached its system, unleashing the personal information of 147-million people. As a result, the company has settled a class action suit ...
Semiconductor Engineering

Advances In Power Management For Physical IP In 28nm And FinFET Process Nodes

Engineering techniques to reduce power consumption by lowering the supply voltage and slowing the clock speed have reached practical limits of the semiconductor technologies. Newer solutions, which ...
EDN

Synopsys Launches Full Range of Silicon-Proven DDR3 and DDR2 IP Solutions for SoC Designs

MOUNTAIN VIEW, Calif., Aug. 13 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing ...