GitHub

Java OpenCL Logic Circuit Simulator

Java OpenCL Logic Circuit Simulator for simulating and debugging fully pipelined binary gate logic. Includes visual designer that also converts OpenCL C code to binary micro-fpga gate logic. Not ...
GitHub

2-Bit Comparator Using Logic Gates

This is a simple project where I built and simulated a 2-bit digital comparator using only basic logic gates in Logisim Evolution. Instead of using the built-in comparator blocks, I created the logic ...
IEEE

SPIN-SIM: logic and fault simulation for speed-independent circuits

Abstract: We present SPIN-SIM, a logic and fault simulator for speed-independent circuits, that extends the classical Eichelberger's method and overcomes its limitations. In order to improve ...
IEEE

First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling

Abstract: This study presents the first functional advanced CFET inverter with an industry-leading 48nm gate pitch, exhibiting well-balanced voltage transfer characteristics up to 1.2 V. In this paper ...